1. Field of the Invention
The present disclosure relates generally to the field of semiconductor packaging, and more particularly, to a multi-chip (or multi-die) semiconductor package utilizing pre-fabricated via components. A method for manufacturing the multi-chip semiconductor package utilizing such pre-fabricated via components is also disclosed.
2. Description of the Prior Art
With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. To reduce the dimensions of such components, the structures by which these components are packaged and assembled with circuit boards must become more compact.
In order to meet the requirements of smaller footprints with higher densities, 3D stacking packaging such as PoP (Package-on-Package) assembly has been developed. Typically, a PoP assembly includes a top package with a semiconductor die bonded to a bottom package with another device die. In PoP designs, the top package is typically interconnected to the bottom package through peripheral solder balls or through mold vias (TMVs).
However, the prior art PoP assembly is not able to provide very tight pitch stacking. Further, the prior art PoP assembly has large package form factor, large package thickness, and poor warpage control. Therefore, there is a need in this industry to provide a fine pitch semiconductor package with reduced form factor and package thickness.